參數(shù)資料
型號： MC68HC11A8BCFN2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 11/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A8BCFN2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
10-10
TECHNICAL DATA
10
ROR (opr)
Rotate Right
EXT
IND,X
IND,Y
A INH
B INH
76
66
18 66
46
56
hh
ll
ff
3
2
3
1
6
7
2
5-8
6-3
7-3
2-1
- - - - ¤ ¤ ¤ ¤
RORA
RORB
RTI
Return from Interrupt
See Special Ops
INH
3B
1
12
2-14
¤
↓ ¤ ¤ ¤ ¤ ¤ ¤
RTS
Return from Subroutine
See Special Ops
INH
39
1
5
2-12
- - - - - - - -
SBA
Subtract B from A
A – B
→ A
INH
10
1
2
2-1
- - - - ¤ ¤ ¤ ¤
SBCA (opr) Subtract with Carry from A
A – M – C
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
82
92
B2
A2
18 A2
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ ¤ ¤
SBCB (opr) Subtract with Carry from B
B – M – C
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C2
D2
F2
E2
18 E2
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ ¤ ¤
SEC
Set Carry
1
→ C
INH
OD
1
2
2-1
- - - - - - - 1
SEI
Set Interrupt Mask
1
→ I
INH
OF
1
2
2-1
- - - 1 - - - -
SEV
Set Overflow Flag
1
→ V
INH
OB
1
2
2-1
- - - - - - 1 -
STAA (opr) Store Accumulator A
A
→ M
A DIR
A EXT
A IND,X
A IND,Y
97
B7
A7
18 A7
dd
hh
ll
ff
2
3
2
3
4
5
4-2
5-3
6-5
7-5
- - - - ¤ ¤ 0 -
STAB (opr) Store Accumulator B
B
→ M
B DIR
B EXT
B IND,X
B IND,Y
D7
F7
E7
18 E7
dd
hh
ll
ff
2
3
2
3
4
5
4-2
5-3
6-5
7-5
- - - - ¤ ¤ 0 -
STD (opr)
Store Accumulator D
A
→ M, B → M + 1
DIR
EXT
IND,X
IND,Y
DD
FD
ED
18 ED
dd
hh
ll
ff
2
3
2
3
4
5
6
4-4
5-5
6-8
7-7
- - - - ¤ ¤ 0 -
STOP
Stop Internal Clocks
INH
CF
1
2
2-1
- - - - - - - -
STS (opr)
Store Stack Pointer
SP
→ M:M + 1
DIR
EXT
IND,X
IND,Y
9F
BF
AF
18 AF
dd
hh
ll
ff
2
3
2
3
4
5
6
4-4
5-5
6-8
7-7
- - - - ¤ ¤ 0 -
STX (opr)
Store Index Register X
IX
→ M:M + 1
DIR
EXT
IND,X
IND,Y
DF
FF
EF
CD EF
dd
hh
ll
ff
2
3
2
3
4
5
6
4-4
5-5
6-8
7-7
- - - - ¤ ¤ 0 -
STY (opr)
Store Index Register Y
IY
→ M:M + 1
DIR
EXT
IND,X
IND,Y
18 DF
18 FF
1A EF
18 EF
dd
hh
ll
ff
3
4
3
5
6
4-6
5-7
6-9
7-7
- - - - ¤ ¤ 0 -
SUBA (opr) Subtract Memory from A
A – M
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
80
90
B0
A0
18 A0
ii
dd
hh
lI
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ ¤ ¤
SUBB (opr) Subtract Memory from B
B – M
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C0
D0
F0
E0
18 E0
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ ¤ ¤
SUBD (opr) Subtract Memory from D
D – M:M + 1
→ D
IMM
DlR
EXT
IND,X
IND,Y
83
93
B3
A3
18 A3
jj
kk
dd
hh
ll
ff
3
2
3
2
3
4
5
6
7
3-3
4-7
5-10
6-10
7-8
- - - - ¤ ¤ ¤ ¤
SWI
Software Interrupt
See Special Ops
INH
3F
1
14
2-15
- - - 1- - - -
TAB
Transfer A to B
A
→ B
INH
16
1
2
2-1
- - - - ¤ ¤ 0 -
TAP
Transfer A to CC Register
A
→ CCR
INH
06
1
2
2-1
¤
↓ ¤ ¤ ¤ ¤ ¤ ¤
TBA
Transfer B to A
B
→ A
INH
17
1
2
2-1
- - - - ¤ ¤ 0 -
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 5 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Bytes
Cycle
by
Cycle*
Condition Codes
Opcode
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
C
b0
b7
C
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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