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參數(shù)資料
| 型號(hào)： | MC68HC11A8BMP2 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 129/158頁 |
| 文件大?。?/td> | 3803K |
| 代理商： | MC68HC11A8BMP2 |
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PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
MC68HC11A8
8-2
TECHNICAL DATA
8
The result obtained by an input capture corresponds to the value of the counter one E
clock cycle after the transition which triggered the edge-detection logic. The selected
edge transition sets the ICxF bit in timer interrupt flag register 1 (TFLG1) and can
cause an interrupt if the corresponding ICxl bit(s) is (are) set in the timer interrupt mask
register 1 (TMSK1). A read of the input capture register’s most significant byte inhibits
captures for one E cycle to allow a double-byte read of the full 16-bit register.
8.1.3 Output Compare
All output compare registers are 16-bit read/write registers which are initialized to
$FFFF by reset. They can be used as output waveform controls or as elapsed time
indicators. If an output compare register is not used, it may be used as a storage loca-
tion.
All output compare registers have a separate dedicated comparator for comparing
against the free-running counter. If a match is found, the corresponding output com-
pare flag (OCxF) bit in TFLG1 is set and a specified action is automatically taken. For
output compare functions two through five the automatic action is controlled by pairs
of bits (OMx and OLx) in the timer control register 1 (TCTL1). Each pair of control bits
are encoded to specify the output action to be taken as a result of a successful OCx
compare. The output action is taken on each successful compare regardless of wheth-
er or not the OCxF flag was previously clear.
An interrupt can also accompany a successful output compare, provided that the cor-
responding interrupt enable bit (OCxl) is set in TMSK1.
After a write cycle to the most significant byte, output compares are inhibited for one
E cycle in order to allow writing two consecutive bytes before making the next compar-
ison. If both bytes of the register are to be changed, a double-byte write instruction
should be used in order to take advantage of the compare inhibit feature.
Writes can be made to either byte of the output compare register without affecting the
other byte.
A write-only register, timer compare force (CFORC), allows forced compares. Five of
the bit positions in the CFORC register correspond to the five output compares. To
force a compare, or compares, a write is done to CFORC register with the associated
bits set for each output compare that is to be forced. The action taken as a result of a
forced compare is the same as if there was a match between the OCx register and the
free-running counter, except that the corresponding interrupt status flag bits are not
set. Output actions are synchronized to the prescaled timer clock so there could be as
much as 16 E clock cycles of delay between the write to CFORC and the output action.
8.1.4 Output Compare 1 I/O Pin Control
Unlike the other four output compares, output compare 1 can automatically affect any
or all of the five output pins (bits 3-7) in port A as a result of a successful compare be-
tween the OC1 register and the 16-bit free-running counter. The two 5-bit registers
used in conjunction with this function are the output compare 1 mask register (OC1M)
and the output compare 1 data register (OC1D).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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