CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-13
10
Table 10-2 Cycle-by-Cycle Operation — Inherent Mode (Sheet 1 of 4)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
2-1
ABA, ASLA, ASLB,
ASRA, ASRB, CBA,
CLC, CLI, CLRA,
CLRB, CLV, COMA,
COMB, DAA, DECA,
DECB, INCA, INCB,
LSLA, LSLB, LSRA,
LSRB, NEGA, NEGB,
NOP, ROLA, ROLB,
RORA, RORB, SBA,
SEC, SEI, SEV, STOP,
TAB, TAP, TBA, TPA,
TSTA, TSTB
21
2
Opcode Address
Opcode Address + 1
1
Opcode
Irrelevant Data
2-2
ABX, ASLD, DEX, INX,
LSLD, LSRD, TXS,
XGDX
31
2
3
Opcode Address
Opcode Address + 1
$FFFF
1
Opcode
Irrelevant Data
2-3
DES, INS, TSX
3
1
2
3
Opcode Address
Opcode Address + 1
Previous SP Value
1
Opcode
Irrelevant Data
2-4
ABY, DEY, INY,
TYS, XGDY
41
2
3
4
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
1
Opcode (Page Select Byte)
($18)
Opcode (Second Byte)
Irrelevant Data
2-5
TSY
4
1
2
3
4
Opcode Address
Opcode Address + 1
Opcode Address + 2
Stack Pointer
1
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($30)
Irrelevant Data
2-6
PSHA, PSHB
3
1
2
3
Opcode Address
Opcode Address + 1
Stack Pointer
1
0
Opcode
Irrelevant Data
Accumulator Data
2-7
PSHX
4
1
2
3
4
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer – 1
1
0
Opcode ($3C)
Irrelevant Data
IXL (Low Byte) to Stack
IXH (High Byte) to Stack
2-8
PSHY
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Opcode Address + 2
Stack Pointer
Stack Pointer – 1
1
0
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($3C)
Irrelevant Data
IXL (Low Byte) to Stack
IXH (High Byte) to Stack
2-9
PULA, PULB
4
1
2
3
4
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer + 1
1
Opcode
Irrelevant Data
Operand Data from Stack
2-10
PULX
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
1
Opcode ($38)
Irrelevant Data
IXH (High Byte) from Stack
IXL (Low Byte) from Stack
* The reference number is given to provide a cross-reference to Table 10-1.
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Freescale Semiconductor, Inc.
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