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參數(shù)資料
| 型號： | MC68HC11A8BVP2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| 封裝： | DIP-48 |
| 文件頁數(shù)： | 81/158頁 |
| 文件大?。?/td> | 776K |
| 代理商： | MC68HC11A8BVP2 |
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MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-1
9
9 RESETS, INTERRUPTS, AND LOW POWER MODES
This section provides a description of the resets, interrupts, and low power modes. The
computer operating properly (COP) watchdog system and clock monitor are described
as part of the reset system. The interrupt description includes a flowchart to illustrate
how interrupts are executed.
9.1 Resets
The MCU has four possible types of reset: an active low external reset pin (RESET),
a power-on reset, a computer operating properly (COP) watchdog timer reset, and a
clock monitor reset.
9.1.1 External RESET Pin
The RESET pin is used to reset the MCU and allow an orderly software start-up pro-
cedure. When a reset condition is sensed, this pin is driven low by an internal device
for four E clock cycles, then released, and two E clock cycles later it is sampled. If the
pin is still low, it means that an external reset has occurred. If the pin is high, it implies
that the reset was initiated internally by either the watchdog timer (COP) or the clock
monitor (refer to
Figure 9-1
). This method of differentiation between internal and ex-
ternal reset conditions assumes that the reset pin will rise to a logic one in less than
two E clock cycles once it is released and that an externally generated reset should
stay active for at least eight E clock cycles.
Since there is EEPROM on chip, it is very important to control reset during power tran-
sitions. If the reset line is not held low while V
DD
is below its minimum operating level,
the EEPROM contents could be corrupted. Corruption occurs due to improper instruc-
tion execution when there is not sufficient voltage to execute instructions correctly.
Both EEPROM memories and the EEPROM based CONFIG register are subject to
this potential problem.
A low voltage inhibit (LVI) circuit which holds reset low whenever V
DD
is below its min-
imum operating level is required to protect against EEPROM corruption.
Figure 9-2
shows an example of reset circuits with LVI capabilities. The best circuit for a particular
application may be different from the suggested circuit.
9.1.2 Power-On Reset
The power-on reset occurs when a positive transition is detected on V
DD
. The power-
on reset is used strictly for power turn-on conditions and should not be used to detect
any drops in power
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