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參數(shù)資料
| 型號(hào)： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 83/158頁(yè) |
| 文件大?。?/td> | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-3
9
Figure 9-2 Simple LVI Reset Circuit
9.1.2.2 Memory Map
After reset, the INIT register is initialized to $01, putting the 256 bytes of RAM at loca-
tions $0000 through $00FF and the control registers at locations $1000 through
$103F. The 8K-byte ROM and/or the 512-byte EEPROM may or may not be present
in the memory map because the two bits that enable them in the CONFIG register are
EEPROM cells and are not affected by reset or power down.
9.1.2.3 Parallel l/O
When a reset occurs in expanded multiplexed operating mode, the 18 pins used for
parallel l/O are dedicated to the expansion bus. If a reset occurs in the single-chip op-
erating mode, the STAF, STAI, and HNDS bits in the parallel input/output control reg-
ister (PIOC) are cleared so that no interrupt is pending or enabled, and the simple
strobed mode (rather than full handshake mode) of parallel l/O is selected. The CWOM
bit in PIOC is cleared so port C is not in wired-OR mode. Port C is initialized as an input
port (DDRC = $00), port B is a general purpose output port with all bits cleared. STRA
is the edge-sensitive strobe A input and the active edge is initially configured to detect
rising edges (EGA bit in the PIOC set), and STRB is the strobe B output and is initially
a logic zero (the INVB bit in the PIOC is set). Port C, port D bits 0 through 5, port A bits
0, 1, 2, and 7, and port E are configured as general purpose high-impedance inputs.
Port B and bits 3 through 6 of port A have their directions fixed as outputs and their
reset state is a logic zero.
9.1.2.4 Timer
During reset, the timer system is initialized to a count of $0000. The prescaler bits are
cleared, and all output compare registers are initialized to $FFFF. All input capture reg-
isters are indeterminate after reset. The output compare 1 mask (OC1M) register is
cleared so that successful OC1 compares do not affect any l/O pins. The other four
output compares are configured to not affect any l/O pins on successful compares. All
three input capture edge-detector circuits are configured for “capture disabled” opera-
tion. The timer overflow interrupt flag and all eight timer function interrupt flags are
cleared. All nine timer interrupts are disabled since their mask bits are cleared.
TO RESET OF 68HC11
(AND OTHER SYSTEM DEVICES)
V
DD
V
DD
MOTOROLA
MC34064
4.7K
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