參數(shù)資料
型號(hào): MC68HC11F1CFN5
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 5 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 122/163頁
文件大小: 711K
代理商: MC68HC11F1CFN5
MC68HC11F1
OPERATING MODES AND ON-CHIP MEMORY
MOTOROLA
TECHNICAL DATA
4-23
Table 4-12 Chip Select Control Parameter Summary
CSIO1
Enable
IO1EN in CSCTL —
1 = On, off at reset (0)
Valid
IO1AV in CSGSIZ —
1 = Address valid, 0 = E valid
Polarity
IO1PL in CSCTL —
1 = Active high, 0 = Active low
Size
Fixed —
($x060–$x7FF)
Start Address
$x060 —
“x” is determined by REG[3:0] in INIT
Stretch
IO1SA–IO1SB in CSSTRH — 0, 1, 2, or 3 E clocks
CSIO2
Enable
IO2EN in CSCTL —
1 = On, off at reset (0)
Valid
IO2AV in CSGSIZ —
1 = Address valid, 0 = E valid
Polarity
IO2PL in CSCTL —
1 = Active high, 0 = Active low
Size
Fixed —
($x800–$xFFF)
Start Address
$x800 —
“x” is determined by REG[3:0] in INIT
Stretch
IO2SA–IO2SB in CSSTRH — 0, 1, 2, or 3 E clocks
CSPROG
Enable
PCSEN in CSCTL —
1 = On, on after reset in expanded modes
off after reset in single-chip modes
Valid
Fixed (Address valid)
Polarity
Fixed (Active low)
Size
PSIZA–PSIZB —
0:0 = 64K ($0000–$FFFF)
in CSCTL
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Start Address
Fixed (determined by size)
Stretch
PSTHA–PSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
1 cycle after reset in expanded mode
no delay after reset in all other modes
Priority
GCSPR in CSCTL —
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
CSGEN
Enable
Set size to 0K to disable —
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
Valid
GAVLD in CSGSIZ —
Address valid or E valid
Polarity
GNPOL in CSGSIZ —
Active high or low
Size
GSIZA–GSIZC in CSGSIZ — Refer to Table 4–12
Start Address
GA[15:10] in CSGADR
Stretch
GSTHA–GSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
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