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參數(shù)資料
| 型號(hào)： | MC68HC11F1CFN5 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 5 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 150/163頁(yè) |
| 文件大小： | 711K |
| 代理商： | MC68HC11F1CFN5 |
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MC68HC11F1
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TECHNICAL DATA
7-1
SECTION 7 SERIAL COMMUNICATIONS INTERFACE
The serial communications interface (SCI) is a universal asynchronous receiver trans-
mitter (UART), one of two independent serial I/O subsystems in the MC68HC11F1
MCU. It has a standard nonreturn to zero (NRZ) format (one start bit, eight or nine data
bits, and one stop bit). Several baud rates are available. The SCI transmitter and re-
ceiver are independent, but use the same data format and bit rate.
7.1 Data Format
The serial data format requires the following conditions:
1. An idle-line in the high state before transmission or reception of a message.
2. A start bit, logic zero, transmitted or received, that indicates the start of each
character.
3. Data that is transmitted and received least significant bit (LSB) first.
4. A stop bit, logic one, used to indicate the end of a frame. (A frame consists of a
start bit, a character of eight or nine data bits, and a stop bit.)
5. A break (defined as the transmission or reception of a logic zero for some mul-
tiple number of frames).
Selection of the word length is controlled by the M bit of SCI control register SCCR1.
7.2 Transmit Operation
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift
register. The contents of the serial shift register can only be written through the SCDR.
This double buffered operation allows a character to be shifted out serially while an-
other character is waiting in the SCDR to be transferred into the serial shift register.
The output of the serial shift register is applied to TxD as long as transmission is in
progress or the transmit enable (TE) bit of serial communication control register 2
(SCCR2) is set. The block diagram, Figure 7-1, shows the transmit serial shift register
and the buffer logic at the top of the figure.
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PDF描述 |
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| MC68HC11F1CPU4R2 | 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| MC68HC11F1CFN3 | 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC11F1CFN2 | 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC11F1VFN2 | 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC11F1MFN3 | 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11F1CFU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1CFU1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1CFU3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1CFU4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1CPU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary 8-Bit Microcontroller |
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