參數(shù)資料
型號： MC68HC11F1CPU4R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-80
文件頁數(shù)： 156/163頁
文件大?。?/td> 711K
代理商： MC68HC11F1CPU4R2
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC11F1
7-6
TECHNICAL DATA
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
T8 — Transmit Data Bit 8
If M bit is set, T8 stores the ninth bit in the transmit data character.
M — Mode (Select Character Format)
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup by Address Mark/Idle
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
7.6.3 Serial Communications Control Register 2
The SCCR2 register provides the control bits that enable or disable individual SCI
functions.
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
ILIE — Idle-Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable
When TE goes from zero to one, one unit of idle character time (logic one) is queued
as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE — Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
SCCR2 — SCI Control Register 2
$102D
Bit 7
654321
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0000000
0
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