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| 型號(hào)： | MC68HC11F1MFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 160/162頁(yè) |
| 文件大?。?/td> | 4554K |
| 代理商： | MC68HC11F1MFN3 |
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SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TECHNICAL DATA
7-11
TDRE and TC flags are normally set when the transmitter is first enabled (TE set to
one). The TDRE flag indicates there is room in the transmit queue to store another
data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIE
is zero, TDRE must be polled. When TIE and TDRE are one, an interrupt is requested.
The TC flag indicates the transmitter has completed the queue. The TCIE bit is the lo-
cal interrupt mask for TC. When TCIE is zero, TC must be polled; when TCIE is one
and TC is one, an interrupt is requested.
Writing a zero to TE requests that the transmitter stop when it can. The transmitter
completes any transmission in progress before actually shutting down. Only an MCU
reset can cause the transmitter to stop and shut down immediately. If TE is written to
zero when the transmitter is already idle, the pin reverts to its general-purpose I/O
function (synchronized to the bit-rate clock). If anything is being transmitted when TE
is written to zero, that character is completed before the pin reverts to general-purpose
I/O, but any other characters waiting in the transmit queue are lost. The TC and TDRE
flags are set at the completion of this last character, even though TE has been dis-
abled.
7.7.1 Receiver Flags
The SCI receiver has five status flags, three of which can generate interrupt requests.
The status flags are set by the SCI logic in response to specific conditions in the re-
ceiver. These flags can be read (polled) at any time by software. Refer to Figure 7–4,
which shows SCI interrupt arbitration.
When an overrun takes place, the new character is lost, and the character that was in
its way in the parallel RDR is undisturbed. RDRF is set when a character has been
received and transferred into the parallel RDR. The OR flag is set instead of RDRF if
overrun occurs. A new character is ready to be transferred into RDR before a previous
character is read from RDR.
The NF and FE flags provide additional information about the character in the RDR,
but do not generate interrupt requests.
The last receiver status flag and interrupt source come from the IDLE flag. The RxD
line is idle if it has constantly been at logic one for a full character time. The IDLE flag
is set only after the RxD line has been busy and becomes idle, which prevents repeat-
ed interrupts for the whole time RxD remains idle.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC11F1MFN4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary 8-Bit Microcontroller |
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| MC68HC11F1MFU4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
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