參數(shù)資料
型號(hào): MC68HC11FC0CFU5
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Technical Summary 8-Bit Microcontroller
中文描述: 8-BIT, 6 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 17/74頁
文件大?。?/td> 513K
代理商: MC68HC11FC0CFU5
MOTOROLA
MC68HC11F1/FC0
24
MC68HC11FTS/D
U = Unaffected by reset
Bits 7:3 — See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.)
NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
These bits can only be written in test and bootstrap modes.
TILOP — Test Illegal Opcode
This test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegal
opcode is fetched.
0 = Normal operation (trap on illegal opcodes)
1 = Inhibit LIR when an illegal opcode is found
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
OCCR — Output Condition Code Register to Timer Port
0 = Normal operation
1 = Condition code bits H, N, Z, V and C are driven on PA[7:3] to allow a test system to monitor
CPU operation
CBYP — Timer Divider Chain Bypass
0 = Normal operation
1 = The 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. The
system E clock drives both halves directly.
DISR — Disable Resets from COP and Clock Monitor
In test and bootstrap modes, this bit is reset to one to inhibit clock monitor and COP resets. In normal
modes, DISR is reset to zero.
0 = Normal operation
1 = COP and Clock Monitor failure do not generate a system reset
FCM — Force Clock Monitor Failure
0 = Normal operation
1 = Generate an immediate clock monitor failure reset. Note that the CME bit in the OPTION register
must also be set in order to force the reset.
FCOP — Force COP Watchdog Failure
0 = Normal operation
1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register
must be cleared (COP enabled) in order to force the reset.
Bit 0 — Not implemented. Reads always return zero and writes have no effect.
CONFIG — EEPROM Mapping, COP, EEPROM Enables
$x03F
Bit 7
654321
Bit 0
EE3
EE2
EE1
EE0
1
NOCOP
1
EEON
RESET
U
U1U1
U
TEST1 — Factory Test
$x03E
Bit 7
6
5
4
3
2
1
Bit 0
TILOP
0
OCCR
CBYP
DISR
FCM
FCOP
0
RESET:
0
0
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