Technical Data
M68HC11K Family
20
List of Figures
MOTOROLA
List of Figures
Figure
Title
Page
9-13
Timer Output Compare
Registers (TOC1–TOC4). . . . . . . . . . . . . . . . . . . . . . . . . .197
Timer Input Capture 4/Output
Compare 5 Register (TI4/O5) . . . . . . . . . . . . . . . . . . . . . .199
Timer Interrupt Flag 1 Register (TFLG1) . . . . . . . . . . . . . . . .199
Timer Interrupt Mask 1 Register (TMSK1) . . . . . . . . . . . . . . .200
Timer Control Register 1 (TCTL1) . . . . . . . . . . . . . . . . . . . . .200
Timer Compare Force Register (CFORC) . . . . . . . . . . . . . . .201
Output Compare 1 Mask Register (OC1M) . . . . . . . . . . . . . .202
Output Compare 1 Data Register (OC1D) . . . . . . . . . . . . . . .202
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . .205
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . .205
Timer Interrupt Flag 2 (TFLG2). . . . . . . . . . . . . . . . . . . . . . . .206
Timer Interrupt Mask 2 (TMSK2) . . . . . . . . . . . . . . . . . . . . . .207
Pulse Accumulator Count Register (PACNT). . . . . . . . . . . . .208
Timer Interrupt Flag 2 Register (TFLG2) . . . . . . . . . . . . . . . .209
Timer Interrupt Mask 2 Register (TMSK2) . . . . . . . . . . . . . . .209
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . .210
Pulse-Width Modulation Timer Block Diagram. . . . . . . . . . . .212
Pulse-Width Modulation Timer Clock Select (PWCLK) . . . . .213
Pulse-Width Modulation Timer
Polarity Register (PWPOL) . . . . . . . . . . . . . . . . . . . . . . . .215
Pulse-Width Modulation Timer
Prescaler Register (PWSCAL). . . . . . . . . . . . . . . . . . . . . .215
Pulse-Width Modulation Timer
Enable Register (PWEN). . . . . . . . . . . . . . . . . . . . . . . . . .216
Pulse-Width Modulation Timer
Counters 1 to 4 (PWCNT1 to PWCNT4) . . . . . . . . . . . . . .217
Pulse-Width Modulation Timer
Periods 1 to 4 (PWPER1 to PWPER4) . . . . . . . . . . . . . . .218
Pulse-Width Modulation Timer
Duty Cycle 1 to 4 (PWDTY1 to PWDTY4). . . . . . . . . . . . .219
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
10-1
10-2
A/D Converter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .222
A/D Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .224
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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