AN1213/D
MOTOROLA
15
M68HC16 IMPLEMENTATION
CODING THE FILTER
The CPU16 can perform signed and unsigned 16-bit integer multiplication as well as signed and unsigned
16-bit fractional multiplication. Since the PID coefficients are neither all-integer nor all-fraction, the values
must be scaled before calculations can be performed, and the same scaling must also be used to correct
the filter output. Because CPU16 DSP instructions use fractional notation, each coefficient is divided by 2,
so that:
P' =
0.08 or
$0A3D
a' =
0.00122 or
$0028
b' =
–0.5123 or
$BE6D
The filter is implemented in an interrupt service routine (ISR) which is called each time the programmable
interrupt timer (PIT) in the SIM times out (every 488
μ
s). The portion of the ISR associated with the PID
implementation is listed at the end of this application note. The complete code can be downloaded from Mo-
torola Freeware Data Systems. Modem connection at (512) 891-3733. Internet address (ftp): free-
ware@aus.sps.mot.com. World-wide web: http://www.freeware.aus.sps.mot.com.
SERVO CONTROL HARDWARE
The MC68HC16Z1EVB provides an excellent platform for this application. Use of CPU16 background de-
bugging mode, the QSM serial communication interface, and the EVB 16-bit DAC are particularly helpful.
Figure 14
is a diagram of the hardware used in the servo system.
The logic to motor interface module (available from Motorola) contains a complementary H-bridge driver
(MPM3002) that is used to provide up to 60 volts to a motor load. The board is operated in four-quadrant
mode (inverted PWM) —the PWM signal that drives one diagonal transistor pair is an inverted version of
the signal that drives the other pair. The PWM interface module prevents excessive heating due to shoot-
through current by delaying each enabling PWM edge approximately 2
μ
s. This provides a switching dead-
band between the time one leg is turned off and the other leg is turned on. The PWM interface module also
uses the current mirror feedback from the MPM3002 to provide cycle-by-cycle current limiting. For further
information about the logic to motor interface module, refer to Interfacing Microcomputers to Fractional
Horsepower Motors(AN1300).
Operating with four-quadrant PWM implies that the waveform generated by the MC68HC16Z1 must be bi-
polar (50% PWM corresponds to no voltage on the motor). As the sample ISR code shows, this is accom-
plished by adding a fixed offset to the digital filter output before it is put in the PWM register. Once the value
is in the PWM register, the general-purpose timer (GPT) generates the required PWM signal without further
CPU intervention.
The 1000-slot encoder on the motor shaft is processed by the Hewlett-Packard HCTL-2016 quadrature de-
coder, which accumulates the encoder count on an internal 16-bit up/down counter. One of the 12
MC68HC16Z1 chip-select outputs is programmed to perform the address decoding necessary to access
and read the HCTL-2016 counter data. 16-bit data is read on data bus pins DATA[15:8] as two sequential
8-bit values. The 16-bit data word is then used to synthesize a 32-bit absolute position variable, as shown
in the beginning of the PID ISR listing.