參數(shù)資料
型號(hào)： MC68HC705J5ACDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 28/106頁
文件大?。?/td> 1069K
代理商： MC68HC705J5ACDWR2
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
INTERRUPTS
MC68HC05J5A
4-2
REV 2.1
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from
the stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occur during interrupt processing.
Figure 4-1. Interrupt Processing Flowchart
4.2
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-1. A low level input on the RESET
pin or an internally generated RST signal causes the program to vector to its start-
ing address which is specied by the contents of memory locations $0FFE and
$0FFF. The I-bit in the condition code register is also set.
Execute
Instruction
From
RESET
Is
I-Bit
Set?
Load PC From:
SWI: $0FFC, $0FFD
IRQ: $0FFA-$0FFB
TIMER: $0FF8-$0FF9
TIMER1: $0FF6-$0FF7
Set I-Bit in CCR
Stack PC, X, A, CC
Clear IRQ
Request
Latch if IRQE1 is
cleared
Restore Registers
from stack
CC, A, X, PC
Y
N
IRQ
External
Interrupt?
Y
N
TIMER
Internal
Interrupt?
Y
N
Fetch Next
Instruction
RTI
Instruction
?
Y
N
SWI
Instruction
?
Y
N
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