參數(shù)資料
型號(hào)： MC68HC705J5ACDWR2
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁(yè)數(shù)： 29/106頁(yè)
文件大?。?/td> 1069K
代理商： MC68HC705J5ACDWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INTERRUPTS
MOTOROLA
REV 2.1
4-3
4.3
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specied by the con-
tents of memory locations $0FFC and $0FFD.
4.4
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
4.5
EXTERNAL INTERRUPT (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ function is shown in Figure 4-2.
Figure 4-2. IRQ Function Block Diagram
IRQ
LATCH
R
VDD
IRQ Pin
IRQE
Mask Option
(IRQ Level)
IRQF
to IRQ
processing
in CPU
IRQR
to BIH & BIL
instruction
sensing
RST
Mask Option
(Port A External Int.)
PA0
PA1
PA2
PA3
IRQ Fetch Vector
IRQE1
IRQ1
LATCH
R
VDD
IRQR1
RST
IRQF1
IRQE1
PA7
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