參數(shù)資料
型號： MC68HC705K1
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： HCMOS Microcontroller Unit
中文描述： HCMOS微控制器
文件頁數(shù)： 69/140頁
文件大?。?/td> 803K
代理商： MC68HC705K1
Parallel Input/Output (I/O)
Port B
MC68HC705K1 — Rev. 2.0
TechnicalData
Parallel Input/Output (I/O)
For More Information On This Product,
Go to: www.freescale.com
is programmed to be an input, reading the port B data register returns
the logic state of the pin. Reset has no effect on port B data.
PB1/OSC3 — Port B Data Bit 1/Oscillator Output Bit
This read/write data bit is software programmable. Data direction
of PB1 bit is under the control of the DDRB1 bit in data direction
register B.
When both the RC and PIN3 bits in the mask option register are set,
PB1/OSC3 can be used as an oscillator output in the 3-pin RC
oscillator configuration. Using PB1/OSC3 as an oscillator output
affects port B in these ways:
a.
Bit PB1 can be used as a read/write storage location without
affecting the oscillator. Reset has no effect on bit PB1.
b.
Bit DDRB1 in data direction register B can be used as a
read/write storage location without affecting the oscillator.
Reset clears DDRB1.
c.
The PB1/OSC3 pulldown device is disabled, regardless of
the state of the SWPDI bit in the mask option register.
PB0 — Port B Data Bit 0
This read/write data bit is software programmable. Data direction of
PB0 is under the control of the DDRB0 bit in data direction register B.
Bits 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
PB1/
OSC3
PB0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
F
Freescale Semiconductor, Inc.
n
.
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參數(shù)描述
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