參數(shù)資料
型號： MC68HC705SR3CFB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 46/96頁
文件大小： 612K
代理商： MC68HC705SR3CFB
MOTOROLA
6-4
MC68HC05SR3
TIMER
6
PR2:PR0
These three bits enable the program to select the division ratio of the prescaler. On reset, these
three bits are set to “100”, which corresponds to a division ratio of 16.
6.3
Timer Data Register (TDR)
The TDR is a read/write register which contains the current value of the 8-bit count-down timer
counter when read. Reading this register does not disturb the counter operation.
6.4
Operation during Low Power Modes
The timer ceases counting in STOP mode. When STOP mode is exited by an external interrupt
(IRQ or IRQ2), the internal oscillator will resume its operation, followed by internal processor
stabilization delay. The timer is then cleared to zero and resumes its operation. The TIF bit in the
TCR will be set. To avoid generating a timer interrupt when exiting STOP mode, it is recommended
to set the TIM bit prior entering STOP mode. After exiting STOP mode TIF bit can then be cleared.
The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are
enabled, the timer interrupt will cause the processor to exit the WAIT mode.
PR2
PR1
PR0
Divide Ratio
000
1
001
2
010
4
011
8
100
16
101
32
110
64
1
128
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$08
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
1111 1111
TPG
48
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