參數(shù)資料
型號(hào)： MC68HC711D3CP3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 116/138頁
文件大?。?/td> 1047K
代理商： MC68HC711D3CP3
Clock Phase and Polarity Controls
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
79
Figure 7-2. SPI Transfer Format
7.4 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI
control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active
high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA)
control bit selects one of two different transfer formats. The clock phase and polarity should be identical
for the master SPI device and the communicating slave device. In some cases, the phase and polarity
are changed between transfers to allow a master device to communicate with peripheral slaves having
different requirements.
When CPHA equals 0, the slave select (SS) line must be negated and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is active
low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
7.5 SPI Signals
This subsection contains description of the four SPI signals:
Master in/slave out (MISO)
Master out/slave in (MOSI)
Serial clock (SCK)
Slave select (SS)
7.5.1 Master In/Slave Out (MISO)
MISO is one of two unidirectional serial data signals. It is an input to a master device and an output from
a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device
is not selected.
2345678
1
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK CYCLE #
SS (TO SLAVE)
6
54321
LSB
MSB
6
54321
LSB
1
2
3
5
4
SLAVE CPHA=1 TRANSFER IN PROGRESS
MASTER TRANSFER IN PROGRESS
SLAVE CPHA=0 TRANSFER IN PROGRESS
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
SAMPLE INPUT
DATA OUT
(CPHA = 0)
SAMPLE INPUT
DATA OUT
(CPHA = 1)
相關(guān)PDF資料
PDF描述
MC68HC11D3CFN3 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44
MC68HC11D3CFB1 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44
MC68L11D0CFB3 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44
MC68HC11D0CFN2R2 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
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