參數(shù)資料
型號： MC68HC711D3CP3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 119/138頁
文件大?。?/td> 1047K
代理商： MC68HC711D3CP3
SPI Registers
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
81
A write collision error occurs if the SPDR is written while a transfer is in progress. Because the SPDR is
not double buffered in the transmit direction, writes to SPDR cause data to be written directly into the SPI
shift register. Because this write corrupts any transfer in progress, a write collision error is generated. The
transfer continues undisturbed, and the write data that caused the error is not written to the shifter.
A write collision is normally a slave error because a slave has no control over when a master initiates a
transfer. A master knows when a transfer is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For a master, a transfer
begins when data is written to SPDR and ends when SPIF is set. For a slave with CPHA equal to zero, a
transfer starts when SS goes low and ends when SS returns high. In this case, SPIF is set at the middle
of the eighth SCK cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to one, transfer begins when
the SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer
ends in a slave in which CPHA equals one when SPIF is set. For a slave, after a byte transfer, SCK must
be in inactive state for at least 2 E-clock cycles before the next byte transfer begins.
7.7 SPI Registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage functions.
This sub-section provides a description of how these registers are organized.
7.7.1 SPI Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Bit
DWOM affects all six port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
Address:
$0028
Bit 7
654321
Bit 0
Read:
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset:
000001
U
U = Unaffected
Figure 7-3. SPI Control Register (SPCR)
相關PDF資料
PDF描述
MC68HC11D3CFN3 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44
MC68HC11D3CFB1 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44
MC68L11D0CFB3 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44
MC68HC11D0CFN2R2 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
MC68HC11D3CP1 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP40
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