
Interrupts
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
87
5.5 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15 maskable interrupts are
generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask
bit (I) in the condition code register (CCR) is clear. The three non-maskable interrupt sources are illegal
opcode trap, software interrupt, and XIRQ pin. Refer to
Table 5-4, which shows the interrupt sources and
vector assignments for each source.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system is
cleared by the automatic clearing mechanism consisting of a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These steps satisfy the automatic clearing mechanism without requiring special
instructions.
Table 5-3. Highest Priority Interrupt Selection
PSEL[3:0]
Interrupt Source Promoted
0 0 0 0
Timer overflow
0 0 0 1
Pulse accumulator overflow
0 0 1 0
Pulse accumulator input edge
0 0 1 1
SPI serial transfer complete
0 1 0 0
SCI serial system
0 1 0 1
Reserved (default to IRQ)
0 1 1 0
IRQ (external pin or parallel I/O)
0 1 1 1
Real-time interrupt
1 0 0 0
Timer input capture 1
1 0 0 1
Timer input capture 2
1 0 1 0
Timer input capture 3
1 0 1 1
Timer output compare 1
1 1 0 0
Timer output compare 2
1 1 0 1
Timer output compare 3
1 1 1 0
Timer output compare 4
1 1 1 1
Timer input capture 4/output compare 5