• 參數(shù)資料
    型號(hào): MC68HC901FN
    廠商: MOTOROLA INC
    元件分類: 外設(shè)及接口
    英文描述: Multi-Function Peripheral
    中文描述: MULTIFUNCTION PERIPHERAL, PQCC52
    封裝: PLASTIC, LCC-52
    文件頁數(shù): 50/73頁
    文件大?。?/td> 274K
    代理商: MC68HC901FN
    Universal Synchronous/Asynchronous Receiver-Transmitter
    7-7
    MC68HC901 USER’S MANUAL
    MOTOROLA
    RE — Receiver Enable
    This bit should not be set until the receiver clock is active. When the transmitter is disabled
    in auto-turnaround mode this bit is set.
    1 = Receiver operation is enabled.
    0 = Receiver is disabled.
    7.2.3 Special Receive Conditions
    Certain receive conditions relating to the overrun error flag and the break detect flag require
    further explanation. Consider the following examples:
    1. A break is received while the receive buffer is full. This does not produce an overrun
    condition. Only the B flag will be set after the receiver buffer is read.
    2. A new word is received, and the receive buffer is full. A break is received before the
    receive buffer is read.
    Both the B and OE flags will be set when the buffer full condition is satisfied.
    7.3 TRANSMITTER
    The transmit buffer is loaded by writing to the USART data register (UDR). The data
    character will be transferred to an internal 8-bit shift register when the last character in the
    shift register has been transmitted. This transfer will produce a buffer empty condition. If the
    transmitter completes the transmission of the character in the shift register before a new
    character is written to the transmit buffer, an underrun error will occur. In the asynchronous
    character format, the transmitter will send a mark until the transmit buffer is written. In the
    synchronous character format, the transmitter will continuously send the synchronous
    character until the transmit buffer is written.
    The transmit buffer can be loaded prior to enabling the transmitter. After the transmitter is
    enabled, there is a delay before the first bit is output. The serial output line (SO) should be
    programmed to be high, low, or high impedance (by setting the appropriate bits in the
    transmitter status register (TSR)) before the transmitter is enabled forcing the output line to
    the desired state until the first bit of the first character is shifted out. The state of the H and
    L bits in the TSR determine the state of the first transmitted bit after the transmitter is
    enabled. If the high impedance mode is selected prior to the transmitter being enabled, the
    first bit transmitted is indeterminate. Note that the SO line will always be driven high for one
    bit time prior to the character in the transmit shift register being transmitted when the
    transmitter is first enabled.
    When the transmitter is disabled, any character currently being transmitted will continue to
    completion. However, any character in the transmit buffer will not be transmitted and will
    remain in the buffer. Thus, no buffer empty condition will occur. If the buffer is empty when
    the transmitter is disabled, the buffer empty condition will remain, but no underrun condition
    will be generated when the character in transmission is completed. If no character is being
    transmitted when the transmitter is disabled, the transmitter will stop at the next rising edge
    of the internal shift clock.
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