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參數(shù)資料
| 型號(hào)： | MC68HC901FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 51/73頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MC68HC901FN |
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Universal Synchronous/Asynchronous Receiver-Transmitter
7-8
MC68HC901 USER’S MANUAL
MOTOROLA
In the asynchronous character format, the transmitter can be programmed to send a break.
The break will be transmitted once the word currently in the shift register has been sent. If
the shift register is empty, the break command will be effective immediately. A transmit error
interrupt will be generated at every normal character boundary to aid in timing the break
transmission. The contents of the TSR are not affected, however. The break will continue
until the break bit is cleared. The underrun error (UE) must be cleared from the TSR. Also,
the interrupt pending register must be cleared of pending transmitter errors at the beginning
of the break transmission, or no interrupts will be generated at the character boundary time.
The break (B) bit cannot be set until the transmitter has been enabled and has had sufficient
time (one transmitter clock cycle) to perform internal reset and initialization functions.
Any character in the transmit buffer at the start of a break will be transmitted when the break
is terminated, assuming the transmitter is still enabled. If the transmit buffer is empty at the
start of a break, it may be written at any time during the break. If the buffer is still empty at
the end of the break, an underrun condition will exist.
Disabling the transmitter during a break condition causes the transmitter to cease
transmission of the break character at the end of the current character. No end-of-break stop
bit will be transmitted. Even if the transmit buffer is empty, no buffer empty condition will
occur nor will an underrun condition occur. Also, any word in the transmit buffer will remain.
7.3.1 Transmitter Interrupt Channels
The USART transmit section is assigned two interrupt channels. The normal channel
indicates a buffer empty condition, and the error channel indicates an underrun or end
condition. These interrupting conditions correspond to the BE, UE, and END flags in the
TSR. The flag bits will function as described in
whether their associated interrupt channel is enabled or disabled.
Section 7.3.2 Transmitter Status Register
7.3.2 Transmitter Status Register (TSR)
The TSR contains various transmitter error flags and transmitter control bits for selecting
auto-turnaround and loopback mode.
BE — Buffer Empty
1 = Character in the transmit buffer transferred to TSR.
0 = Transmit buffer reloaded by writing to the USR.
U — Underrun Error
One full transmitter clock cycle is required after UE bit is set before it can be cleared. This
bit does not require clearing before writing to the UDR.
TSR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
BE
UE
AT
END
B
H
L
TE
RESET
0
0
0
0
0
0
0
0
ADDR
$2D
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