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| 型號： | MC68HC901FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 32/73頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MC68HC901FNR2 |
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MOTOROLA
MC68HC901 USER’S MANUAL
6-1
SECTION 6
TIMERS
The MFP contains four 8-bit timers which provide many functions typically required in
microprocessor systems. The timers can supply the baud rate clocks for the on-chip serial
I/O channel, generate periodic interrupts, measure elapsed time, and count signal
transitions. In addition, two timers have waveform generation capability.
All timers are prescaler/counter timers with a common independent clock input (XTAL1 and
XTAL2). Each timer's output signal toggles when the timer's main counter times out.
Additionally, timers A and B have auxiliary control signals (TAI, TBI) which are used in two
of the operation modes. An interrupt channel is assigned to each timer, and when the
auxiliary control signals are used in the pulse width measurement mode, a separate interrupt
channel will respond to transitions on these inputs.
6.1 OPERATION MODES
Timers A and B are full function timers which, in addition to the delay mode, operate in the
pulse width measurements mode and the event count mode. Timers C and D are delay
timers only. A brief discussion of each of the timer modes follows.
6.1.1 Delay Mode Operation
All timers may operate in the delay mode. In this mode, the prescaler is always active. The
prescaler specifies the number of timer clock cycles which must elapse before a count pulse
is applied to the main counter. A count pulse causes the main counter to decrement by one.
When the timer has decremented down to 01 (hexadecimal), the next count pulse will cause
the main counter to be reloaded from the timer data register and a time out pulse will be
produced. This time out pulse is coupled to the timer's interrupt channel and, if the channel
is enabled, an interrupt will occur. The time out pulse also causes the timer output pin to
toggle. The output will remain in this new state until the next time out pulse occurs.
For example, if delay mode with a divide-by-10 prescaler is selected and the timer data
register is loaded with 100 (decimal), the main counter will decrement once every 10 timer
clock cycles. After 1000 timer clocks, a time out pulse will be produced. This time out pulse
will generate an interrupt if the channel is enabled (IERA, IERB), and in addition, the timer's
output line will toggle. The output line will complete one full period every 2000 cycles of the
timer clock.
If the prescaler value is changed while the timer is enabled, the first time out pulse will occur
at an indeterminate time no less than one or more than 200 timer clock cycles. Subsequent
time out pulses will then occur at the correct interval.
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