Timer Interface Module (TIM2)
Data Sheet
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
280
Timer Interface Module (TIM2)
MOTOROLA
18.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described
changing the pulse width requires writing the new pulse width value over the value
currently in the TIM2 channel registers.
An unsynchronized write to the TIM2 channel registers to change a pulse width
value could cause incorrect operation for up to two PWM periods. For example,
writing a new value before the counter reaches the old value but after the counter
reaches the new value prevents any compare during that PWM period. Also, using
a TIM2 overflow interrupt routine to write a new, smaller pulse width value may
cause the compare to be missed. The TIM2 may pass the new value before it is
written to the timer channel (T2CHxH:T2CHxL) registers.
Use the following methods to synchronize unbuffered changes in the PWM pulse
width on channel x:
When changing to a shorter pulse width, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current pulse. The
interrupt routine has until the end of the PWM period to write the new value.
When changing to a longer pulse width, enable TIM2 overflow interrupts and
write the new value in the TIM2 overflow interrupt routine. The TIM2
overflow interrupt occurs at the end of the current PWM period. Writing a
larger value in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same PWM period.
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation
and removes the ability of the channel to self-correct in the event of software error
or noise. Toggling on output compare also can cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
18.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output
appears on the T2CH0 pin. The TIM2 channel registers of the linked pair
alternately control the pulse width of the output.
Setting the MS0B bit in TIM2 channel 0 status and control register (T2SC0) links
channel 0 and channel 1. The TIM2 channel 0 registers initially control the pulse
width on the T2CH0 pin. Writing to the TIM2 channel 1 registers enables the TIM2
channel 1 registers to synchronously control the pulse width at the beginning of the
next PWM period. At each subsequent overflow, the TIM2 channel registers
(0 or 1) that control the pulse width are the ones written to last. T2SC0 controls and
monitors the buffered PWM function, and TIM2 channel 1 status and control
register (T2SC1) is unused. While the MS0B bit is set, the channel 1 pin, T2CH1,
is available as a general-purpose I/O pin.