參數(shù)資料
型號(hào)： MC68HCL05C12AB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： PLASTIC, SDIP-42
文件頁數(shù)： 115/156頁
文件大小： 756K
代理商： MC68HCL05C12AB
Timer
Timer During Wait Mode
MC68HC05C12A — Rev. 3.0
General Release Specification
MOTOROLA
Timer
61
NON-DISCLOSURE
AGREEMENT
REQUIRED
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set.
2. The LSB of the free-running counter is read but not for the purpose
of servicing the flag.
The counter alternate register at addresses $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
8.8 Timer During Wait Mode
The CPU clock halts during wait mode, the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
the wait mode.
8.9 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if
stop is exited by an interrupt. If reset is used, the counter is forced to
$FFFC. During stop, if at least one valid input capture edge occurs at the
TCAP pin, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU. But if the MCU exits stop due to an
external interrupt, there is an active input capture flag and data from the
first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid
input capture edge occurred.
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