參數(shù)資料
型號(hào): MC68HCL05C4AFN
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 29/156頁
文件大小: 992K
代理商: MC68HCL05C4AFN
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specications
General Release Specification
MC68HC05C4A Rev. 4.0
124
Electrical Specifications
Figure 13-5. External Interrupt Timing
Figure 13-6. External Reset Timing
NORMALLY
USED WITH
WIRED-OR
IRQ
t
ILIH
t
ILIL
t
ILIH
IRQ PIN
IRQ1
IRQn
.
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t
ILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (f
OP = 1 MHz). The period tILIL should not be less than the number of t
cyc cycles it takes to
execute the interrupt service routine plus 19 tcyc cycles.
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt
is recognized.
INTERNAL
CLOCK1
INTERNAL
ADDRESS BUS1
NOTES:
INTERNAL
DATA BUS1
1FFE
1FFF
NEW PC
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
t
RL
NEW
PCL
OP
CODE
RESET2
1FFE
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