參數(shù)資料
型號(hào): MC68HCP11A1VFN
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 470 PF 5% 100V NPO (0805) CHIP CAP
中文描述: 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁(yè)數(shù): 12/45頁(yè)
文件大小: 286K
代理商: MC68HCP11A1VFN
MOTOROLA
12
MC68HC11A8
MC68HC11A8TS/D
Test Modes Only
TILOP — Test Illegal Opcode
OCCR — Output Condition Code Register to Timer Port
CBYP — Timer Divider Chain Bypass
DISR — Disable Resets from COP and Clock Monitor
DISR is forced to one out of reset in special test and bootstrap modes.
FCM — Force Clock Monitor Failure
FCOP — Force COP Watchdog Failure
TCON — Test Configuration Register
NOTE
The bits of this register are implemented with EEPROM cells. Programming and
erasing follow normal EEPROM procedures. The erased state of CONFIG is $0F.
A new value is not readable until after a subsequent reset sequence. CONFIG can
only be programmed or erased in special modes.
NOSEC — EEPROM Security Disable
Refer to
4 Electrically Erasable Programmable Read-Only Memory (EEPROM)
.
NOCOP — COP System Disable
Refer to
3 Resets and Interrupts
.
ROMON — ROM Enable
In single-chip mode, ROMON is forced to one out of reset.
0 = 8K ROM removed from the memory map
1 = 8K ROM present in the memory map
EEON — EEPROM Enable
0 = EEPROM is removed from the memory map
1 = EEPROM is present in the memory map
TEST1
— Factory Test
$103E
Bit 7
TILOP
0
6
0
0
5
4
3
2
1
Bit 0
TCON
0
OCCR
0
CBYP
0
DISR
FCM
0
FCOP
0
RESET:
CONFIG
— COP, ROM, EEPROM Enables
$103F
Bit 7
0
0
6
0
0
5
0
0
4
0
0
3
2
1
Bit 0
EEON
NOSEC
NOCOP
ROMON
RESET:
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