參數(shù)資料
型號: MC68HCP11A1VFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 470 PF 5% 100V NPO (0805) CHIP CAP
中文描述: 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 15/45頁
文件大?。?/td> 286K
代理商: MC68HCP11A1VFN
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
15
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
CME — Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
CR1, CR0 — COP Timer Rate Select
Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP
watchdog.
RBOOT — Read Bootstrap ROM Bits 7–4
Refer to
2 Operating Modes and Memory Maps
.
SMOD — Special Mode Select
Refer to
2 Operating Modes and Memory Maps
.
MDA — Mode Select A
Refer to
2 Operating Modes and Memory Maps
.
IRV — Internal Read Visibility
Refer to
2 Operating Modes and Memory Maps
.
PSEL[3:0] — Priority Select Bits 3 through 0
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to be elevated above all other I-bit related sources.
CR [1:0]
Divide
E/2
By
1
4
16
64
E =
15
XTAL = 4.0 Mhz
Timeout
–0/+32.8 ms
32.768 ms
131.072 ms
524.288 ms
2.097 sec
1.0 MHz
XTAL = 8.0 MHz
Timeout
–0/+16.4 ms
16.384 ms
65.536 ms
262.140 ms
1.049 sec
2.0 MHz
XTAL = 12.0 MHz
Timeout
–0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
0 0
0 1
1 0
1 1
COPRST
— Arm/Reset COP Timer Circuitry
$103A
Bit 7
7
0
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
0
0
RESET:
HPRIO
— Highest Priority I-Bit Interrupt and Miscellaneous
$103C
Bit 7
RBOOT
6
5
4
3
2
1
Bit 0
PSEL0
1
SMOD
MDA
IRV
PSEL3
0
PSEL2
1
PSEL1
0
RESET:
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