System Integration Module (SIM)
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
116
System Integration Module (SIM)
MOTOROLA
Figure 13-6. Sources of Internal Reset
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR)
generates a pulse to indicate that power on has occurred. The SIM counter counts
out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive BUSCLKX4.
Internal clocks to the CPU and modules are held inactive for 4096
BUSCLKX4 cycles to allow stabilization of the oscillator.
The POR bit of the SIM reset status register (SRSR) is set.
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP
counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR). The SIM actively pulls down the RST pin for all internal reset
sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to
location $FFFF clears the COP counter and stages 12–5 of the SIM counter. The
SIM counter output, which occurs at least every (212 – 24) BUSCLKX4 cycles,
drives the COP counter. The COP should be serviced as soon as possible out of
reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when
BDCOP bit is set in break auxiliary register (BRKAR).
Table 13-2. Reset Recovery Timing
Reset Recovery Type
Actual Number of Cycles
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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