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參數資料
| 型號： | MC68HLC908QT1DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 69/186頁 |
| 文件大?。?/td> | 2765K |
| 代理商： | MC68HLC908QT1DW |
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Development Support
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
160
Development Support
MOTOROLA
15.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin
requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce
circuit requirements when performing in-circuit programming.
NOTE:
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset vector
has been programmed, the traditional method of applying a voltage, VTST, to IRQ
must be used to enter monitor mode.
If monitor mode was entered as a result of the reset vector being blank, the COP
is always disabled regardless of the state of IRQ.
If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset
in user mode. Internal circuitry monitors the reset vector fetches and will assert an
internal reset if it detects that the reset vectors are erased ($FF). When the MCU
comes out of reset, it is forced into monitor mode without requiring high voltage on
the IRQ pin. Once out of reset, the monitor code is initially executing with the
internal clock at its default frequency.
If IRQ is held high, all pins will default to regular input port functions except for
PTA0 and PTA5 which will operate as a serial communication port and OSC1 input
respectively (refer to Figure 15-12). That will allow the clock to be driven from an
external source through OSC1 pin.
If IRQ is held low, all pins will default to regular input port function except for PTA0
which will operate as serial communication port. Refer to Figure 15-13.
Regardless of the state of the IRQ pin, it will not function as a port input pin in
monitor mode. Bit 2 of the Port A data register will always read 0. The BIH and BIL
instructions will behave as if the IRQ pin is enabled, regardless of the settings in
the configuration register. See Section 5. Configuration Register (CONFIG).
The COP module is disabled in forced monitor mode. Any reset other than a
power-on reset (POR) will automatically force the MCU to come back to the forced
monitor mode.
15.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt),
and break interrupt than those for user mode. The alternate vectors are in the $FE
page instead of the $FF page and allow code execution from the internal monitor
firmware instead of user code.
NOTE:
Exiting monitor mode after it has been initiated by having a blank reset vector
requires a power-on reset (POR). Pulling RST (when RST pin available) low will
not exit monitor mode in this situation.
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