參數(shù)資料
型號(hào)： MC68HSC05C12ACFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 104/156頁
文件大?。?/td> 3848K
代理商： MC68HSC05C12ACFB
Input/Output (I/O) Ports
Port D
MC68HC05C12A — Rev. 3.0
General Release Specification
Input/Output (I/O) Ports
NON-DISCLOSURE
AGREEMENT
REQUIRED
7.6 Port D
Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI
subsystem, two more are shared with the SCI subsystem. Reset does
not affect the data registers. During reset, all seven bits become valid
input ports because all special function output drivers associated with
the SCI, timer, and SPI subsystems are disabled.
7.7 Input/Output Programming
I/O port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all I/O pins
as inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin. For further information, refer to Table 7-1 and Figure 7-2.
Table 7-1. I/O Pin Functions
R/W*
DDR
I/O Pin Function
00
The I/O pin is in input mode. Data is written into the output
data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
*R/W is an internal signal.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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