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參數(shù)資料
| 型號： | MC68HSC05C12ACFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 123/156頁 |
| 文件大?。?/td> | 3848K |
| 代理商： | MC68HSC05C12ACFB |
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Serial Communications Interface (SCI)
SCI Operation
MC68HC05C12A — Rev. 3.0
General Release Specification
Serial Communications Interface (SCI)
NON-DISCLOSURE
AGREEMENT
REQUIRED
9.5.2.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCCR1) determines character length.
When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8).
9.5.2.2 Character Reception
During reception, the receive shift register shifts characters in from the
PD0/RDI pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character is transferred to the SCDR, setting the receive
data register full (RDRF) flag. The RDRF flag can be used to generate
an interrupt.
9.5.2.3 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup enable (RWU) bit in SCI
control register 2 (SCCR2) puts the receiver into a standby state during
which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the receiver out of
the standby state:
1. Idle input line condition — If the PD0/RDI pin is at logic one long
enough for 10 or 11 logic ones to shift into the receive shift
register, receiver interrupts are again enabled.
2. Address mark — If a logic one occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
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For More Information On This Product,
Go to: www.freescale.com
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