Instruction Set
Opcode Map
MC68HC05C8A
—
Rev. 3.0
General Release Specification
MOTOROLA
Instruction Set
111
L
G
R
12.6 Opcode Map
See
Table 12-7.
SWI
Software Interrupt
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
— 1 — — —
INH
83
10
TAX
Transfer Accumulator to Index Register
X
←
(A)
— — — — —
INH
97
2
TST opr
TSTA
TSTX
TST oprX
TST ,X
Test Memory Byte for Negative or Zero
(M) – $00
— —
¤
¤
—
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
3
5
4
TXA
Transfer Index Register to Accumulator
A
←
(X)
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
A
C
CCR Condition code register
dd
Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR
Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
ff
Offset byte in indexed, 8-bit offset addressing
H
Half-carry flag
hh ll
High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
IMM Immediate addressing mode
INH
Inherent addressing mode
IX
Indexed, no offset addressing mode
IX1
Indexed, 8-bit offset addressing mode
IX2
Indexed, 16-bit offset addressing mode
M
Memory location
N
Negative flag
n
Any bit
Accumulator
Carry/borrow flag
opr
PC
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
Relative program counter offset byte
rr
Relative program counter offset byte
SP
Stack pointer
X
Index register
Z
Zero flag
#
Immediate value
∧
Logical AND
∨
Logical OR
⊕
Logical EXCLUSIVE OR
( )
Contents of
–( )
Negation (two’s complement)
←
Loaded with
If
:
Concatenated with
¤
Set or cleared
—
Not affected
Operand (one or two bytes)
Program counter
Table 12-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
H I N Z C