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參數(shù)資料
| 型號(hào)： | MC68HSC05C8AFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 39/116頁(yè) |
| 文件大?。?/td> | 781K |
| 代理商： | MC68HSC05C8AFB |
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MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
29
Chapter 4
Interrupts
4.1 Introduction
The microcontroller unit (MCU) can be interrupted five different ways:
Four maskable hardware interrupts, IRQ (interrupt request), SPI (serial peripheral interface),
SCI (serial communications interface), and timer
Non-maskable software interrupt instruction (SWI)
Port B interrupts, if enabled, are combined with the IRQ to form a single interrupt source.
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit)
to prevent additional interrupts. The RTI (return to interrupt) instruction causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but they are
considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all pending hardware interrupts. If
interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the
external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of
the I-bit state.
Vector addresses for all interrupts, including reset, are listed in Table 4-1.
4.2 Hardware Controlled Interrupt Sequence
Three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts; however, they are
acted upon in a similar manner. Flowcharts for hardware interrupts are shown in Figure 4-1.
1.
RESET — A low input on the RESET input pin causes the program to vector to its starting address,
which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a known state during this type of reset,
as previously described in Chapter 5 Resets.
2.
STOP — The STOP instruction causes the oscillator to be turned off and the processor to “sleep”
until an external interrupt
(IRQ) or reset occurs.
3.
WAIT — The WAIT instruction causes all processor clocks to stop, but leaves the timer clock
running. This “rest” state of the processor can be cleared by reset, an external interrupt (IRQ),
serial peripheral interface, serial communications interface, or timer interrupt. These individual
interrupts have no special wait vectors.
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