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參數(shù)資料
| 型號： | MC68HSC05C8AFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 47/116頁 |
| 文件大?。?/td> | 781K |
| 代理商： | MC68HSC05C8AFB |
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Low-Power Modes
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
36
Freescale Semiconductor
6.2 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest-power consumption mode. In
stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation.
During stop mode, the TCR bits are altered to remove any pending timer interrupt request and to disable
any further timer interrupts. The timer prescaler is cleared. The I bit in the condition code register is
cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output
lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or
reset.
6.3 Stop Recovery
The processor can be brought out of stop mode only by an external interrupt or reset. See Figure 6-2.
6.4 Wait Mode
The WAIT instruction places the MCU in a low-power consumption mode, but the wait mode consumes
more power than the stop mode. All CPU action is suspended, but the timer, serial communications
interface (SCI), serial peripheral interface (SPI), and the oscillator remain active. Any interrupt or reset will
cause the MCU to exit wait mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer may be enabled to allow a periodic exit from
wait mode.
Figure 6-2. Stop Recovery Timing Diagram
1FFE
1FFF
INTERNAL ADDRESS BUS
INTERNAL CLOCK
IRQ
(3)
IRQ
(2)
RESET
OSC1
(1)
t
ILCH
4064 t
cyc
RESET ($1FFE, $1FFF) OR
INTERRUPT ($1FFA, $1FFB)
VECTOR FETCH
t
ILIH
t
RL
Notes:
1.
Represents the internal gating of the OSC1 pin
2.
IRQ pin edge-sensitive option
3.
IRQ pin level and edge sensitive option
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