參數(shù)資料
型號: MC68HSC05C8CB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
封裝: SHRINK, PLASTIC, DIP-42
文件頁數(shù): 127/166頁
文件大?。?/td> 1914K
代理商: MC68HSC05C8CB
Timer
Input Capture Register
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
Technical Data
MOTOROLA
Timer
63
Figure 8-2. Output Compare Operation
8.5 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register except when exiting stop
mode.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
16-BIT COMPARATOR
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
COUNTER HIGH BYTE
TCMP
PIN
CONTROL
LOGIC
TIMER
INTERRUPT
REQUEST
COUNTER LOW BYTE
15
0
15
8 7
0
TIMER STATUS REGISTER
$0013
TIMER CONTROL REGISTER
$0012
IC
IE
OCIE
TO
IE
IC
F
OCF
TO
F
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