參數(shù)資料
型號: MC68HSC05C8CB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
封裝: SHRINK, PLASTIC, DIP-42
文件頁數(shù): 129/166頁
文件大?。?/td> 1914K
代理商: MC68HSC05C8CB
Timer
Timer Control Register
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
Technical Data
MOTOROLA
Timer
65
8.6 Timer Control Register
l Register
The timer control register (TCR) is a read/write register containing five
control bits. Three bits control interrupts associated with the timer status
register flags ICF, OCF, and TOF.
ICIE — Input Capture Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge Bit
Value of input edge determines which level transition on TCAP pin will
trigger free-running counter transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit.
OLVL — Output Level Bit
Value of output level is clocked into output level register by the next
successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
Address:
$0012
Bit 7
654321
Bit 0
Read:
ICIE
OCIE
TOIE
0
IEDG
OLVL
Write:
Reset:
000000
U
0
U = Unaffected
Figure 8-4. Timer Control Register (TCR)
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