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參數(shù)資料
| 型號(hào)： | MC68HSC05C8CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 41/116頁 |
| 文件大?。?/td> | 781K |
| 代理商： | MC68HSC05C8CFN |
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Interrupts
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
30
Freescale Semiconductor
4.3 Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt. It is executed
regardless of the state of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after
interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
4.4 External Interrupt (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled.
Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge
of IRQ. It is then synchronized internally and serviced as specified by the contents of $1FFA and $1FFB.
When any of the port B pullups are enabled, that pin becomes an additional external interrupt source
which is coupled to the IRQ pin logic. It follows the same edge/edge-level selection that the IRQ pin has.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger operation is
selectable by mask option.
NOTE
The internal interrupt latch is cleared in the first part of the interrupt service
routine; therefore, one external interrupt pulse could be latched and
serviced as soon as the I bit is cleared.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag Name
Interrupts
CPU Interrupt
Vector Address
N/A
Reset
RESET
$1FFE–$1FFF
N/A
Software
SWI
$1FFC–$1FFD
N/A
External interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
Timer input capture
TIMER
$1FF8–$1FF9
TSR
OCF
Timer output compare
TIMER
$1FF8–$1FF9
TSR
TOF
Timer overflow
TIMER
$1FF8–$1FF9
SCSR
TDRE
Transmit buffer empty
SCI
$1FF6–$1FF7
SCSR
TC
Transmit complete
SCI
$1FF6–$1FF7
SCSR
RDRF
Receiver buffer full
SCI
$1FF6–$1FF7
SCSR
IDLE
Idle line detect
SCI
$1FF6–$1FF7
SCSR
OR
Overrun
SCI
$1FF6–$1FF7
SPSR
SPIF
Transfer complete
SPI
$1FF4–$1FF5
SPSR
MODF
Mode fault
SPI
$1FF4–$1FF5
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