參數(shù)資料
型號: MC68HSR705J1ACS
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, MICROCONTROLLER, CDIP20
封裝: WINDOWED, CERAMIC, DIP-20
文件頁數(shù): 94/162頁
文件大小: 3213K
代理商: MC68HSR705J1ACS
Memory
RAM
MC68HC705J1A — Rev. 4.0
Technical Data
Memory
2.5 RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM and
the stack RAM. Before processing an interrupt, the central processor
unit (CPU) uses five bytes of the stack to save the contents of the CPU
registers. During a subroutine call, the CPU uses two bytes of the stack
to store the return address. The stack pointer decrements when the CPU
stores a byte on the stack and increments when the CPU retrieves a byte
from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
$0019
Unimplemented
$001E
Unimplemented
$001F
Reserved
RRRRRRRR
$07F0
COP Register
(COPR)
Read:
Write:
COPC
Reset:
0
$07F1
Mask Option Register
(MOR)
Read:
SOSCD
EPMSEC OSCRES
SWAIT
SWPDI
PIRQ
LEVEL
COPEN
Write:
Reset:
Unaffected by reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
R = Reserved
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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