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參數資料
| 型號： | MC68L11D0FN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 82/131頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | MC68L11D0FN2 |
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MOTOROLA
RESETS AND INTERRUPTS
MC68HC11D3
5-10
TECHNICAL DATA
5.4.2 Non-Maskable Interrupt Request XIRQ
Non-maskable interrupts are useful because they can always interrupt CPU opera-
tions. The most common use for such an interrupt is for serious system problems, such
as program runaway or power failure. The XIRQ input is an updated version of the
nonmaskable NMI input of earlier MCUs.
Upon reset, both the X bit and I bits of the CCR are set to inhibit all maskable interrupts
and XIRQ. After minimum system initialization, software can clear the X bit by a TAP
instruction, enabling XIRQ interrupts. Thereafter, software cannot set the X bit. Thus,
an XIRQ interrupt is a nonmaskable interrupt. Because the operation of the I-bit-relat-
ed interrupt structure has no effect on the X bit, the internal XIRQ pin remains non-
masked. In the interrupt priority logic, the XIRQ interrupt has a higher priority than any
source that is maskable by the I bit. All I-bit-related interrupts operate normally with
their own priority relationship.
When an I-bit-related interrupt occurs, the I bit is automatically set by hardware after
stacking the CCR byte. The X bit is not affected. When an X-bit-related interrupt oc-
curs, both the X and I bits are automatically set by hardware after stacking the CCR.
A return from interrupt instruction restores the X and I bits to their pre-interrupt request
state.
5.4.3 Illegal Opcode Trap
Because not all possible opcodes or opcode sequences are defined, the MCU in-
cludes an illegal opcode detection circuit, which generates an interrupt request. When
an illegal opcode is detected and the interrupt is recognized, the current value of the
program counter is stacked. After interrupt service is complete, reinitialize the stack
pointer so repeated execution of illegal opcodes does not cause stack underflow. Left
uninitialized, the illegal opcode vector can point to a memory location that contains an
illegal opcode. This condition causes an infinite loop that causes stack underflow. The
stack grows until the system crashes.
The illegal opcode trap mechanism works for all unimplemented opcodes on all four
opcode map pages. The address stacked as the return address for the illegal opcode
interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be
almost impossible to determine whether the illegal opcode had been one or two bytes.
Table 5-5 Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP
PCL
SP – 1
PCH
SP –2
IYL
SP – 3
IYH
SP – 4
IXL
SP – 5
IXH
SP – 6
ACCA
SP – 7
ACCB
SP – 8
CCR
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| MC68L11E0FNE2 | 功能描述:IC MCU 8BIT LV 512RAM 52-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 標準包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設備:- 輸入/輸出數:32 程序存儲器容量:8KB（8K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數據轉換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285 |
| MC68L11E1CFNE2 | 功能描述:8位微控制器 -MCU 8B MCU RAM EE A/D LVDC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68L11E1FNE2 | 功能描述:8位微控制器 -MCU 8B MCU RAM EE A/D LVD RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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