參數(shù)資料
型號: MC68MH360VR25L
廠商: Freescale Semiconductor
文件頁數(shù): 125/158頁
文件大小: 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 44
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
QMC Supplement
4.4 Channel Interrupt Processing Flow
Figure 4-5 illustrates the ow of a channel interrupt. Note that this does not describe the
processing of the global interrupts GUN and GOV.
14
TXB
Tx buffer
0 = No TXB event has occurred.
1 = A buffer has been completely transmitted. This bit is set (and an interrupt request is
generated) as soon as the programmed number of PAD characters (or the closing ag, for
PAD = 0) is written to the SCC’s transmit FIFO. The number of PAD characters determines
the timing of the TXB interrupt in relation to the closing ag sent out at TXD. See
Chapter 5, “Buffer Descriptors,” for an explanation of PAD characters and their use.
15
RXB
Rx buffer
0 = No RXB event has occurred.
1 = A buffer has been received on this channel.
Table 4-2. Interrupt Table Entry Field Descriptions (Continued)
Field
Name
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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