參數(shù)資料
型號: MC68MH360VR25LR2
廠商: Freescale Semiconductor
文件頁數(shù): 113/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
QMC Supplement
2.4.2.5 RSTATE—Rx Internal State (Transparent Mode)
The RSTATE is host-initialized before enabling the channel or after a fatal error (that is,
global overrun, busy) or after a STOP Rx command.
The high byte of RSTATE denes the function code/address type and the Motorola/Intel bit.
Bit 3 (or bit 29 for the 68360) should always be set to 1. Figure 2-15 shows the RSTATE
register for transparent mode.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-15. RSTATE—Rx Internal State (Transparent Mode)
For the MH360, RSTATE should be initialized to 0x3900_0000 before enabling the
channel—function code 9. Table 2-14 describes the RSTATE elds for the MH360 with
boldfaced parameters to be initialized by the user.
01234567
0
1
MOT
FC[3–0]/ AT[1–3]
Table 2-14. RSTATE Field Descriptions for MH360 (Transparent Mode)
Field
Name
Description
0–1
0
2—
1
3
MOT
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
4–7
FC[3–0]
Function code—This eld contains the function code for the transmitter DMA channel for
data buffers in external memory (transmit buffers). Function codes are needed by the
memory controller to decode a correct memory cycle and activate the correct handshaking.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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