參數(shù)資料
型號: MC68MH360VR25LR2
廠商: Freescale Semiconductor
文件頁數(shù): 55/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
QMC Supplement
C.3.2 MC145572 U Interface
The FREQREF signal of the MC145572 provides a clock synchronized to the network
timing for the U interface. This frequency reference is a xed 2.048-MHz clock enabled by
setting OR8[4] in the MC145572 register set.
The U interface’s FREQREF differs from the TCLK of the S/T interface. When enabled,
the FREQREF signal generates the 2.048-MHz clock regardless of the activation status of
the U interface (but that clock is synchronized to the network only when the U interface is
activated). Also, FREQREF does not require the DCL and FSC signals to enable clock
generation.
Like the S/T interface, on the other hand, the FREQREF signal can be used as the DCL for
the IDL bus. When divided by 256, FREQREF can also be used to generate the 8-KHz
frame sync FSC. The same logic design used for the S/T interface must be added to insure
a correct FSC duty cycle; see Figure C-4.
Also like the S/T interface, elastic buffers are included to allow the U interface to operate
with any phase relationship between the IDL frame sync and the network.
Figure C-10 shows a block diagram of the connection between four U interfaces and the
QUICC32. The diagram would be the same for up to 10 U interfaces.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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