參數(shù)資料
型號(hào): MC705P6AMPE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 31/98頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8BIT 4.5K FLASH 28-PDIP
標(biāo)準(zhǔn)包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 4.5KB(4.5K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
37
Chapter 6
Input/Output Ports
6.1 Introduction
In the user mode, 20 bidirectional I/O lines are arranged as two 8-bit I/O ports (ports A and C), one 3-bit
I/O port (port B), and one 1-bit I/O port (port D). These ports are programmable as either inputs or outputs
under software control of the data direction registers (DDRs). Port D also contains one input-only pin.
6.2 Port A
Port A is an 8-bit bidirectional port, which does not share any of its pins with other subsystems (see
Figure 6-1). The port A data register is located at address $0000 and its data direction register (DDR) is
located at address $0004. The contents of the port A data register are indeterminate at initial power up
and must be initialized by user software. Reset does not affect the data registers, but does clear the
DDRs, thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding
port pin to output mode. Port A has mask option register enabled interrupt capability with an internal pullup
device
NOTE
The keyscan (pullup/interrupt) feature available on port A is NOT available
in the ROM device, MC68HC05P6.
Figure 6-1. Port A I/O and Interrupt Circuitry
READ $0000
WRITE $0000
READ $0004
DATA
REGISTER BIT
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0004
DATA DIRECTION
REGISTER BIT
TO IRQ
INTERRUPT SYSTEM
VDD
PULLUP MASK
OPTION REGISTER
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