參數(shù)資料
型號(hào): MC7457RX733NC
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 28/71頁(yè)
文件大?。?/td> 0K
描述: IC MPU RISC 32BIT 483FCCBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 733MHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 483-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 483-FCCBGA(29x29)
包裝: 托盤
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Electrical and Thermal Characteristics
Freescale Semiconductor
34
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
Figure 15. TRST Timing Diagram
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
20
25
ns
4
Output hold times:
Boundary-scan data
TDO
tJLDX
tJLOX
30
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see Figure 13).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
tTCLK
VM
VM = Midpoint Voltage (OVDD/2)
tJR
tJF
tJHJL
TCLK
TRST
tTRST
VM = Midpoint Voltage (OVDD/2)
VM
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