參數(shù)資料
型號: MC7457VG867NC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483
封裝: 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-483
文件頁數(shù): 4/73頁
文件大?。?/td> 1715K
代理商: MC7457VG867NC
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
12
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 2. Overshoot/Undershoot Voltage
The MPC7457 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see
Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied
to the OVDD or GVDD power pins.
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input Threshold
is Relative to:
L3VSEL Signal 1
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
2, 3
HRESET
Not Available
HRESET
1.5 V
2, 4
HRESET
2.5 V
HRESET
2.5 V
2
1
2.5 V
1
2.5 V
2
Notes:
1. Not implemented on MPC7447.
2. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.
3. If used, pull-down resistors should be less than 250
Ω.
4. Applicable to L3 bus interface only. HRESET is the inverse of HRESET.
VIH
GND
GND – 0.3 V
GND – 0.7 V
Not to exceed 10%
OVDD/GVDD + 20%
VIL
OVDD/GVDD
OVDD/GVDD + 5%
of tSYSCLK
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