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參數(shù)資料
| 型號： | MC74HC280D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-Bit Odd/Even Parity Generator/Checker |
| 中文描述： | HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 205K |
| 代理商： | MC74HC280D |
MC74HC280
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 2)
4.5
41
62
6.0
13
51
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
60
pF
PIN DESCRIPTIONS
INPUTS
A, B, C, D, E, F, G, H, I (Pins 8–13, 1, 2, 4)
Nine–bit data–word inputs. The data word placed on these
pins is checked for even or odd parity.
OUTPUTS
Even Parity (Pin 5)
Even–parity output. This pin goes high if the data word has
even parity and low if the data word has odd parity.
Odd Parity (Pin 6)
Odd–parity output. This pin goes high if the data word has
odd parity and low if the data word has even parity.
Figure 1. Switching Waveforms
Figure 2. Test Circuit
PARITY OUTPUT
tPHL
tTHL
tTLH
tPLH
GND
VCC
tf
tr
90%
50%
10%
10%
90%
DATA INPUT
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
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