參數(shù)資料
型號: MC74HC563A
廠商: Motorola, Inc.
英文描述: Octal 3-State Inverting Transparent Latch
中文描述: 八路三態(tài)反相透明鎖存器
文件頁數(shù): 4/8頁
文件大小: 207K
代理商: MC74HC563A
MC54/74HC563A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Symbol
b l
Parameter
25 C
U i
6.0
20
– 55 to
125
75
26
20
125 C
30
tPHL
6.0
(Figures 1 and 5)
3.0
24
70
30
95
25
110
tPHL
6.0
6.0
(Figures 2 and 5)
3.0
75
38
35
95
25
115
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
10
60
155
80
33
190
100
ns
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
125
75
155
80
30
190
100
ns
Maximum Output Transition Time, Any Output
2.0
6.0
15
75
13
90
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance
15
15
pF
CPD
Power Dissipation Capacitance (Per Latch)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
40
pF
(Input tr = tf = 6 ns)
Parameter
V
VCC
25 C
10
9
11
125 C
Guaranteed Limit
3
– 55 to
1000
800
500
4.5
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
4.5
60
15
13
16
Minimum Hold Time, Latch Enable to Input D
(Figure 4)
3
3
Minimum Pulse Width, Latch Enable
(Figure 2)
3.0
4.5
75
19
90
22
Maximum Input Rise and Fall Times
(Figure 1)
4.5
500
500
相關(guān)PDF資料
PDF描述
MC74HC563ADW 0.5A Bridge Rectifier; Package: SOIC; No of Pins: 4; Container: Tape & Reel
MC74HC563AN 0.5A Bridge Rectifier
MC74HC563 Octal 3-State Inverting Transparent Latch
MC74HC563DW 0.5A Bridge Rectifier; Package: SOIC; No of Pins: 4; Container: Tape & Reel
MC74HC563N Octal 3-State Inverting Transparent Latch
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