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參數(shù)資料
| 型號： | MC74HC563DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 0.5A Bridge Rectifier; Package: SOIC; No of Pins: 4; Container: Tape & Reel |
| 中文描述： | HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 222K |
| 代理商： | MC74HC563DW |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74HC563 is identical in pinout to the LS563. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC533 but has the Data Inputs on
the opposite side of the package from the outputs to facilitate PC board
layout.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears at the outputs
in inverted form. When Latch Enable goes low, data meeting the setup and
hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC573 is the noninverting version of this function.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAM
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
INVERTING
OUTPUTS
DATA
INPUTS
11
1
LATCH
ENABLE
OUTPUT
ENABLE
PIN 20 = VCC
PIN 10 = GND
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
VCC
LATCH
ENABLE
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs
Latch
Enable
Output
Output
Enable
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
L
H
No Change
Z
X = don’t care
Z = high impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74HC563N | Octal 3-State Inverting Transparent Latch |
| MC74HC564 | Octal 3-State Inverting D Flip-Flop |
| MC74HC564DW | Octal 3-State Inverting D Flip-Flop |
| MC74HC564N | Octal 3-State Inverting D Flip-Flop |
| MC74HC76 | Dual JK Flip-Flop With Set and Reset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74HC564ADW | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| MC74HC564AF | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC564AFL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC564AN | 制造商:ON Semiconductor 功能描述: |
| MC74HC573ADT | 功能描述:閉鎖 2-6V Transparent RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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