參數(shù)資料
型號(hào): MC74HC564DW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Octal 3-State Inverting D Flip-Flop
中文描述: HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20
封裝: 0.300 INCH, PLASTIC, SOIC-20
文件頁(yè)數(shù): 1/6頁(yè)
文件大?。?/td> 193K
代理商: MC74HC564DW
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC564 is identical in pinout to the LS564. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC534A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
Data meeting the setup time is clocked, in inverted form, to the outputs
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip–flops, but when Output Enable is high, all device outputs are
forced to the high–impedance state. Thus, data may be stored even when
the outputs are not enabled.
The HC564 is the inverting version of the HC574A.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 282 FETs or 70.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
2
19
Q0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT
ENABLE
3
4
5
6
7
8
9
11
1
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
VCC
CLOCK
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs
Output
Output
Enable
Clock
D
Q
L
L
L
H
H
L
X
X
L
H
L,H,
No Change
Z
X
X = don’t care
Z = high impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXDW
Plastic
SOIC
1
20
1
20
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