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參數(shù)資料
| 型號(hào)： | MC74HC76D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK Flip-Flop With Set and Reset |
| 中文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | MC74HC76D |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC76 is identical in pinout to the LS76. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
Each flip–flop is negative–edge clocked and has active–low asynchro-
nous Set and Reset inputs.
The HC76 is identical in function to the HC112, but has a different
pinout.
Similar in Function to the LS76 Except When Set and Reset Are
Low Simultaneously
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 100 FETs or 25 Equivalent Gates
15
Q1
2
Set1
PIN 5 = VCC
PIN 13 = GND
LOGIC DIAGRAM
16
K1
1
Clock1
4
J1
3
Reset1
14
Q1
11
Q2
7
Set2
12
K2
6
Clock2
9
J2
8
Reset2
10
Q2
FUNCTION TABLE
Inputs
Outputs
Set
Reset
Clock
J
K
Q
Q
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
H
L
L*
No Change
L
H
Toggle
No Change
No Change
No Change
L
H
L*
H
L
L
H
* Both outputs will remain low as long as Set and Reset are low, but the output states are
unpredictable if Set and Reset go high simultaneously.
16
1
15
2
14
3
13
4
K1
Clock1
12
5
11
6
10
7
9
8
Q1
Set1
Q1
Reset1
GND
J1
K2
VCC
Q2
Clock2
Q2
Set2
J2
Reset2
Pinout: 16–Lead Packages
(Top View)
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
1
16
1
16
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